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UltraSoC extends on-chip analytics architecture for the age of machine learning, artificial intelligence and parallel computing

UltraSoC today announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.

The new features allow SoC designers to build on-chip monitoring and analytics systems with up to 65,000 elements, allowing seamless support for systems with many thousands of processors. Future iterations will allow even higher numbers of processors for Exascale systems. In addition to this dramatically improved scaling capability, new System Memory Buffer (SMB) IP allows the embedded analytics infrastructure to handle the high volumes of data generated by multicore systems, and to cope with “bursty” real-world traffic.

The new UltraSoC architecture is capable of monitoring effectively unlimited numbers of the internal building blocks that make up the most complex SoC products – and to analyze the impact on system-level behavior of the interactions between them. Such heterogeneous multicore chips are becoming increasingly common, particularly in enabling the artificial intelligence and machine learning technologies required in leading edge applications such as driverless cars.

Dave Ditzel, Founder and CEO of Esperanto, commented: “Esperanto’s mission is to enable the most energy-efficient high-performance computing systems for artificial intelligence, machine learning and other emerging applications. That requires us to put over a thousand RISC-V processors and AI/ML accelerators on a single chip; UltraSoC’s ability to match that level of scaling with monitoring, analytics and debug capabilities is a vital enabler for our business.”

UltraSoC CEO, Rupert Baines, said: “Our solutions are unique in the market in their ability to deal with multiple heterogeneous processors, standard and proprietary bus structures and even custom logic. This dramatic extension of our architecture takes us even further ahead of traditional solutions – both in the debug and development arena, and in allowing our customers to incorporate in-life monitoring capabilities to ensure security, functional safety and real-world performance optimization.”

UltraSoC’s system-level monitoring and analytics capabilities extend beyond the chip’s core processing components to all parts of the system – which may include thousands of IP blocks and subsystems, buses, interconnects and software. The new features within the UltraSoC architecture allow chip designers to deploy tens of thousands of monitoring and analytics modules within a single infrastructure. By providing an integrated, coherent analysis of the behavior of the system, UltraSoC significantly reduces the development burden for next-generation machine learning and artificial intelligence applications, as well as allowing the implementation of innovative product features such as hardware-based security and functional safety.

Extension of the UltraSoC architecture to encompass effectively unlimited monitoring capabilities helps developers to address the problems of systemic complexity which are among the most pressing issues faced by the electronics industry today. In addition to the sheer size of modern SoCs, machine learning and artificial intelligence algorithms are often inherently non-deterministic: because they devise their own ways of solving problems by ‘learning’, it is impossible for the system’s original designer to predict how they will behave in the final application. In-life monitoring of the chip’s behavior is therefore the only way of getting a true picture of what is going on inside the chip, and the wider system.

The complex interactions between multiple hardware blocks, firmware and software within SoCs have already made real-time in-life monitoring an indispensable tool for SoC designers. Changes in design approaches are also making system-wide monitoring more necessary than ever. Agile software development and ad hoc programming practices inherently require high-granularity visibility of the real system. Similarly, system hardware and software may not be ‘architected’ in the traditional sense: again, engineers need clear visibility of the run-time behavior of their systems.

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eSilicon builds momentum as a strong tier one FinFET ASIC supplier

eSilicon, a provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company’s growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.

Critical requirements to serve these markets include leading-edge, high-performance, differentiating semiconductor IP that is validated in advanced process nodes, a track record of successful design and fabrication of complex, FinFET-class ASICs and expertise in the design and manufacture of 2.5D package assemblies, including the integration of HBM memory stacks.

In the fall of last year, eSilicon announced availability of its neuASIC™ IP platform for AI ASIC design. The innovative IP platform includes an HBM2 PHY and AI mega/giga cells, including a convolution engine and accelerator builder software, all verified in 7nm technology. In that same time frame, the company announced that its 56G long-reach 7nm DSP SerDes was available for licensing.

In January, 2019, eSilicon announced a new high-performance test system to facilitate customer validation of its SerDes IP. At the recent DesignConshow, eSilicon demonstrated the new test system and its SerDes driving a five-meter copper cable at 56Gbps with very low error rates. Several customer engagements are underway with this SerDes IP, and customer feedback is validating its best-in-class capabilities. Also in January, eSilicon announced the formation of a technical advisory board for its AI initiatives staffed by three prominent technologists from academia and industry.

The company is in active production bring-up with two FinFET designs, including 2.5D technology utilizing its HBM2 PHY. All performance parameters are being met and both designs are on track to achieve full-scale production this year. One of the designs represents the largest ASIC eSilicon has ever built. It is believed to be the largest chip the foundry has ever produced as well.

“Our customers demand best-in-class IP, advanced ASIC and packaging expertise and the resources and technical depth to facilitate production bring-up of the final device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “I am pleased to say we are delivering on all fronts. Recently, a tier one customer reported that they were usually quite critical of all IP. They went on to say they could find nothing to criticize after detailed evaluation of our SerDes.”

eSilicon will be presenting “A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET” at ISSCC in San Francisco on February 18. The company will be demonstrating its SerDes live at ISSCC that day as well. You can also find eSilicon at OFC in San Diego from March 5-7 (booth #5416), where the company will present two high-speed SerDes demonstrations and a demonstration if its HBM2 PHY.

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Samsung SDS and IBM collaborate to strengthen open source hyperledger fabric and blockchain ecosystems

During IBM THINK 2019, IBM’s annual conference focused on technology and business, Samsung SDS announced it is continuing its collaboration with IBM in support of advancing Hyperledger Fabric, an open source cross-industry blockchain technology, with recent code contributions, research and a new white paper.

As a contributor to Hyperledger Fabric, Samsung SDS is working to improve fabric capabilities and actively contributing its new “Accelerator” code to the open source community. The new code is expected to significantly improve Hyperledger Fabric performance for specific use cases.

Samsung SDS is also making a new white paper available, “Accelerating Throughput in Permissioned Blockchain Networks,” co-written by IBM. The paper validates the applicability of Accelerator to Hyperledger Fabric, provides a roadmap and also illustrates performance improvement in terms of transactions per second. A copy of the white paper and the Innovation Sandbox environment is now available for external developers to test. (https://github.com/nexledger/accelerator)

While this technical initiative is being rigorously validated from the open source Hyperledger community, Samsung SDS will prepare to become IBM’s key go-to-market reseller partner of IBM Blockchain Platform in Korea.

Ted Kim, Vice President, Blockchain Team from Samsung SDS America has been named to the IBM Blockchain Board of Advisors. Additionally, during the IBM Think Conference in San Francisco, Kiwoon Sung, Head of Blockchain Research Lab, Samsung SDS, will discuss the company’s blockchain innovation efforts at a session entitled, “New Blockchain Solutions emerging from the IBM Blockchain ecosystem.”

Hyperledger is an open source collaborative effort created to advance cross-industry blockchain technologies. It is a global collaboration including leaders in finance, banking, Internet of Things, supply chains, manufacturing and Technology. The Linux Foundation hosts Hyperledger under the foundation. To learn more, visit: https://www.hyperledger.org/.

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Cadence selected as primary EDA tool vendor by GLOBALFOUNDRIES

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that GLOBALFOUNDRIES (GF) has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has come to rely on the features, capacity, speed and scalability of the Cadence® digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows. Establishing Cadence as their primary vendor has enabled them to improve engineering productivity.

Avera Semi has successfully completed several large, complex 12nm and 14nm tapeouts and delivered production designs using Cadence flagship solutions such as the Innovus™ Implementation System, the Genus™Synthesis Solution, the Tempus™ Timing Signoff Solution and Xcelium™Parallel Logic Simulation as well as the Virtuoso® custom IC design platform, Spectre® circuit simulation platform and Allegro® and Sigrity™tools, which are part of following product categories:

  • Digital and Signoff: The parallelized, integrated Cadence digital and signoff solutions provided Avera Semi with a trusted design flow to achieve industry-leading power, performance and area (PPA) results with integrated signoff accuracy for designs with more than 500M instances, complex clocking requirements and chip sizes at the mask reticle limit.
  • System and Verification: The Cadence Verification Suite helped the Avera Semi verification team find bugs more efficiently, quickly implement and bring up complex testbenches for faster project completion and fuel testbench automation, analysis and reuse for increased productivity.
  • Custom IC/Analog Design: The comprehensive analog and mixed-signal simulation capabilities in the Cadence custom IC design platform enabled Avera Semi to consistently, accurately and quickly design and verify complex IP such as the Avera Semi 112G Serial Link. Additionally, the tight integration of Cadence physical verification and design-for-manufacturing (DFM) tools within the Cadence Virtuoso IC design platform accelerated design and implementation.
  • PCB Design and Analysis: Cadence’s PCB design and analysis tools helped Avera Semi achieve a smooth and efficient interface between the chip and packaging teams, helping to manage and track engineering change requests. The tools’ customizability enabled Avera Semi to automate the numerous properties associated with a package, reducing manual errors and design cycle time.

“Today’s announcement is another solid step in our collaborative journey to achieve a higher level of productivity through Cadence’s design flow,” said Kevin O’Buckley, GM at Avera Semi. “We have already deployed the Cadence flows to complete a number of successful production designs for our customers using the GF 12nm and 14nm FinFET process technologies and will extend our collaboration with Cadence on advanced nodes. Standardizing on Cadence’s custom, digital and IC package flows and verification solutions will help us master new challenges encountered at advanced nodes and expand our leadership in designs for data centers, wired communications, and machine learning and artificial intelligence applications.”

“Avera Semi uses Cadence as its primary supplier due to many years of successful collaborations on large, complex designs that met evolving market demands,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We are always working to optimize design flow speed, throughput and provide differentiated tool features to deliver best-in-class PPA to customers. As we expand upon our longstanding relationship with Avera Semi, their customers can also benefit from our continued innovation and dedication to advancing ASIC design.”

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Molecular Lego blocks

Producing traditional solar cells made of silicon is very energy intensive. On top of that, they are rigid and brittle. Organic semiconductor materials, on the other hand, are flexible and lightweight. They would be a promising alternative, if only their efficiency and stability were on par with traditional cells.

Together with his team, Karsten Reuter, Professor of Theoretical Chemistry at the Technical University of Munich, is looking for novel substances for photovoltaics applications, as well as for displays and light-emitting diodes – OLEDs. The researchers have set their sights on organic compounds that build on frameworks of carbon atoms.

Both the carbon-based molecular frameworks and the functional groups decisively influence the conductivity of organic semiconductors. Researchers at the Technical University of Munich (TUM) now deploy data mining approaches to identify promising organic compounds for the electronics of the future. Credit: C. Kunkel / TUM

Contenders for the electronics of tomorrow

Depending on their structure and composition, these molecules, and the materials formed from them, display a wide variety of physical properties, providing a host of promising candidates for the electronics of the future.

“To date, a major problem has been tracking them down: It takes weeks to months to synthesize, test and optimize new materials in the laboratory,” says Reuter. “Using computational screening, we can accelerate this process immensely.”

Computers instead of test tubes

The researcher needs neither test tubes nor Bunsen burners to search for promising organic semiconductors. Using a powerful computer, he and his team analyze existing databases. This virtual search for relationships and patterns is known as data mining.

“Knowing what you are looking for is crucial in data mining,” says PD Dr. Harald Oberhofer, who heads the project. “In our case, it is electrical conductivity. High conductivity ensures, for example, that a lot of current flows in photovoltaic cells when sunlight excites the molecules.”

Algorithms identify key parameters

Using his algorithms, he can search for very specific physical parameters: An important one is, for example, the “coupling parameter.” The larger it is, the faster electrons move from one molecule to the next.

A further parameter is the “reorganization energy”: It defines how costly it is for a molecule to adapt its structure to the new charge following a charge transfer – the less energy required, the better the conductivity.

The research team analyzed the structural data of 64,000 organic compounds using the algorithms and grouped them into clusters. The result: Both the carbon-based molecular frameworks and the “functional groups”, i.e. the compounds attached laterally to the central framework, decisively influence the conductivity.

Identifying molecules using artificial intelligence

The clusters highlight structural frameworks and functional groups that facilitate favorable charge transport, making them particularly suitable for the development of electronic components.

“We can now use this to not only predict the properties of a molecule, but using artificial intelligence we can also design new compounds in which both the structural framework and the functional groups promise very good conductivity,” explains Reuter.

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Spintronics by ‘straintronics’

Switching magnetic domains in magnetic memories requires normally magnetic fields which are generated by electrical currents, hence requiring large amounts of electrical power. Now, teams from France, Spain and Germany have demonstrated the feasibility of another approach at the nanoscale: “We can induce magnetic order on a small region of our sample by employing a small electric field instead of using magnetic fields”, Dr. Sergio Valencia, HZB, points out.

The cones represents the magnetization of the nanoparticles. In the absence of electric field (strain-free state) the size and separation between particles leads to a random orientation of their magnetization, known as superparamagnetism. Credit: HZB

The samples consist of a wedge-shaped polycrystalline iron thin film deposited on top of a BaTiO3 substrate. BaTiO3 is a well-known ferroelectric and ferroelastic material: An electric field is able to distort the BaTiO3 lattice and induce mechanical strain. Analysis by electron microscopy revealed that the iron film consists of tiny nanograins (diameter 2,5 nm). At its thin end, the iron film is less than 0,5 nm thick, allowing for “low dimensionality” of the nanograins. Given their small size, the magnetic moments of the iron nanograins are disordered with respect to each other, this state is known as superparamagnetism.

At the X-PEEM-Beamline at BESSY II, the scientists analysed what happens with the magnetic order of this nanograins under a small electric field. “With X-PEEM we can map the magnetic order of the iron grains on a microscopic level and observe how their orientation changes while in-situ applying an electric field”, Dr. Ashima Arora explains, who did most of the experiments during her PhD Thesis. Their results show: the electrical field induced a strain on BaTiO3, this strain was transmitted to the iron nanograins on top of it and formerly superparamagnetic regions of the sample switched to a new state. In this new state the magnetic moments of the iron grains are all aligned along the same direction, i.e. a collective long-range ferromagnetic order known as superferromagnetism.

The experiments were performed at a temperature slightly above room temperature. “This lets us hope that the phenomenon can be used for the design of new composite materials (consisting of ferroelectric and magnetic nanoparticles) for low-power spin-based storage and logic architectures operating at ambient conditions”, Valencia says.

Controlling nanoscale magnetic bits in magnetic random access memory devices by electric field induced strain alone, is known also as straintronics. It could offer a new, scalable, fast and energy efficient alternative to nowadays magnetic memories.

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Emerald picks Lonza for cannabinoid synthesis

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UltraSoC extends on-chip analytics architecture for the age of machine learning, artificial intelligence and parallel computing

UltraSoC today announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.

The new features allow SoC designers to build on-chip monitoring and analytics systems with up to 65,000 elements, allowing seamless support for systems with many thousands of processors. Future iterations will allow even higher numbers of processors for Exascale systems. In addition to this dramatically improved scaling capability, new System Memory Buffer (SMB) IP allows the embedded analytics infrastructure to handle the high volumes of data generated by multicore systems, and to cope with “bursty” real-world traffic.

The new UltraSoC architecture is capable of monitoring effectively unlimited numbers of the internal building blocks that make up the most complex SoC products – and to analyze the impact on system-level behavior of the interactions between them. Such heterogeneous multicore chips are becoming increasingly common, particularly in enabling the artificial intelligence and machine learning technologies required in leading edge applications such as driverless cars.

Dave Ditzel, Founder and CEO of Esperanto, commented: “Esperanto’s mission is to enable the most energy-efficient high-performance computing systems for artificial intelligence, machine learning and other emerging applications. That requires us to put over a thousand RISC-V processors and AI/ML accelerators on a single chip; UltraSoC’s ability to match that level of scaling with monitoring, analytics and debug capabilities is a vital enabler for our business.”

UltraSoC CEO, Rupert Baines, said: “Our solutions are unique in the market in their ability to deal with multiple heterogeneous processors, standard and proprietary bus structures and even custom logic. This dramatic extension of our architecture takes us even further ahead of traditional solutions – both in the debug and development arena, and in allowing our customers to incorporate in-life monitoring capabilities to ensure security, functional safety and real-world performance optimization.”

UltraSoC’s system-level monitoring and analytics capabilities extend beyond the chip’s core processing components to all parts of the system – which may include thousands of IP blocks and subsystems, buses, interconnects and software. The new features within the UltraSoC architecture allow chip designers to deploy tens of thousands of monitoring and analytics modules within a single infrastructure. By providing an integrated, coherent analysis of the behavior of the system, UltraSoC significantly reduces the development burden for next-generation machine learning and artificial intelligence applications, as well as allowing the implementation of innovative product features such as hardware-based security and functional safety.

Extension of the UltraSoC architecture to encompass effectively unlimited monitoring capabilities helps developers to address the problems of systemic complexity which are among the most pressing issues faced by the electronics industry today. In addition to the sheer size of modern SoCs, machine learning and artificial intelligence algorithms are often inherently non-deterministic: because they devise their own ways of solving problems by ‘learning’, it is impossible for the system’s original designer to predict how they will behave in the final application. In-life monitoring of the chip’s behavior is therefore the only way of getting a true picture of what is going on inside the chip, and the wider system.

The complex interactions between multiple hardware blocks, firmware and software within SoCs have already made real-time in-life monitoring an indispensable tool for SoC designers. Changes in design approaches are also making system-wide monitoring more necessary than ever. Agile software development and ad hoc programming practices inherently require high-granularity visibility of the real system. Similarly, system hardware and software may not be ‘architected’ in the traditional sense: again, engineers need clear visibility of the run-time behavior of their systems.

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eSilicon builds momentum as a strong tier one FinFET ASIC supplier

eSilicon, a provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company’s growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.

Critical requirements to serve these markets include leading-edge, high-performance, differentiating semiconductor IP that is validated in advanced process nodes, a track record of successful design and fabrication of complex, FinFET-class ASICs and expertise in the design and manufacture of 2.5D package assemblies, including the integration of HBM memory stacks.

In the fall of last year, eSilicon announced availability of its neuASIC™ IP platform for AI ASIC design. The innovative IP platform includes an HBM2 PHY and AI mega/giga cells, including a convolution engine and accelerator builder software, all verified in 7nm technology. In that same time frame, the company announced that its 56G long-reach 7nm DSP SerDes was available for licensing.

In January, 2019, eSilicon announced a new high-performance test system to facilitate customer validation of its SerDes IP. At the recent DesignConshow, eSilicon demonstrated the new test system and its SerDes driving a five-meter copper cable at 56Gbps with very low error rates. Several customer engagements are underway with this SerDes IP, and customer feedback is validating its best-in-class capabilities. Also in January, eSilicon announced the formation of a technical advisory board for its AI initiatives staffed by three prominent technologists from academia and industry.

The company is in active production bring-up with two FinFET designs, including 2.5D technology utilizing its HBM2 PHY. All performance parameters are being met and both designs are on track to achieve full-scale production this year. One of the designs represents the largest ASIC eSilicon has ever built. It is believed to be the largest chip the foundry has ever produced as well.

“Our customers demand best-in-class IP, advanced ASIC and packaging expertise and the resources and technical depth to facilitate production bring-up of the final device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “I am pleased to say we are delivering on all fronts. Recently, a tier one customer reported that they were usually quite critical of all IP. They went on to say they could find nothing to criticize after detailed evaluation of our SerDes.”

eSilicon will be presenting “A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET” at ISSCC in San Francisco on February 18. The company will be demonstrating its SerDes live at ISSCC that day as well. You can also find eSilicon at OFC in San Diego from March 5-7 (booth #5416), where the company will present two high-speed SerDes demonstrations and a demonstration if its HBM2 PHY.

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Samsung SDS and IBM collaborate to strengthen open source hyperledger fabric and blockchain ecosystems

During IBM THINK 2019, IBM’s annual conference focused on technology and business, Samsung SDS announced it is continuing its collaboration with IBM in support of advancing Hyperledger Fabric, an open source cross-industry blockchain technology, with recent code contributions, research and a new white paper.

As a contributor to Hyperledger Fabric, Samsung SDS is working to improve fabric capabilities and actively contributing its new “Accelerator” code to the open source community. The new code is expected to significantly improve Hyperledger Fabric performance for specific use cases.

Samsung SDS is also making a new white paper available, “Accelerating Throughput in Permissioned Blockchain Networks,” co-written by IBM. The paper validates the applicability of Accelerator to Hyperledger Fabric, provides a roadmap and also illustrates performance improvement in terms of transactions per second. A copy of the white paper and the Innovation Sandbox environment is now available for external developers to test. (https://github.com/nexledger/accelerator)

While this technical initiative is being rigorously validated from the open source Hyperledger community, Samsung SDS will prepare to become IBM’s key go-to-market reseller partner of IBM Blockchain Platform in Korea.

Ted Kim, Vice President, Blockchain Team from Samsung SDS America has been named to the IBM Blockchain Board of Advisors. Additionally, during the IBM Think Conference in San Francisco, Kiwoon Sung, Head of Blockchain Research Lab, Samsung SDS, will discuss the company’s blockchain innovation efforts at a session entitled, “New Blockchain Solutions emerging from the IBM Blockchain ecosystem.”

Hyperledger is an open source collaborative effort created to advance cross-industry blockchain technologies. It is a global collaboration including leaders in finance, banking, Internet of Things, supply chains, manufacturing and Technology. The Linux Foundation hosts Hyperledger under the foundation. To learn more, visit: https://www.hyperledger.org/.

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